Many microprocessor systems include memory management hardware to provide protection, isolation, and abstraction between software and physical memory. One typical addressing scheme includes the use of virtual memory that require dividing physical memory into a number of fixed size page frames and mapping virtual pages into those pages through a page mapping table. Different types and/or sizes of pages may be provided. To increase the speed of the translation process, microprocessors typically keep a cache of recently translated pages in a translation lookaside buffer (TLB).
Another type of memory management is segmentation which supports a number of segments of configurable size and start address. Segmentation is typically implemented via the use of segment registers implicitly specified in the instruction, which contains an index into a segment mapping table in memory that contains a segment descriptor. Segment descriptor caches have been developed to accelerate the translation process. There is a small number of segment registers that hold the actual contents of a few entries of the segment mapping table.
Although existing solutions solve the basic problem of mapping from a virtual to a physical address space and providing per page protection (or per segment protection in case of segmentation), they require high speed local lookup tables to provide a rapid address translation. These tables are relatively complex to manage since they are a form of caches of larger structures and are typically implemented as associative structures that have significant area and power costs associated with them. In addition, in the case of segmentation, since there is a small number of segment registers, using more than several segments is cumbersome as it requires an expensive segment register load.